Clock signals are used to coordinate actions of electrical circuits in electrical circuit devices. In some devices, these signals can be single-ended clock signals where a signal is transmitted by a voltage and is referenced to a fixed potential (e.g., a ground node). In such devices, one conductor carries the clock signal while another conductor carries the reference potential. Other electrical circuit devices can use a differential clock signal that employs two complementary (e.g., inverse) voltage signals to transmit one information signal. A receiver in such devices extracts information by detecting the potential difference between the complementary voltage signals. Each complementary voltage signal is carried by its own conductor, which means that differential-signaling often requires more wires than single-ended signaling and, thus, more space. Despite this disadvantage, differential signaling has many benefits over single-ended signaling. For example, because the two voltage signals have equal amplitude and opposite polarity relative to a common-mode voltage, return currents and electromagnetic interference generated by each signal are balanced and cancel each other out, which is an advantage especially noticeable at high frequencies. This, in turn, also reduces crosstalk to other nearby signals. In addition, electromagnetic interference or crosstalk introduced by outside sources is often added to each voltage signal, so the magnitude of the interference or crosstalk is reduced when a receiver takes a potential difference between the two signals. Furthermore, differential signaling provides a more straightforward logic state determination procedure, allows for more precise timing, and maintains an adequate signal-to-noise ratio at lower voltages. Even so, neither type of clock signaling is immune to duty cycle distortion.
A duty cycle of a clock signal is a ratio of the pulse time of the clock signal to its cycle period. A duty cycle of a clock signal can become distorted due to a variety of sources, including amplifiers that make up a clock tree, large propagation distances between amplifier stages of the clock tree, and/or parasitic conductor capacitance. Distortion of the duty cycle skews timing margins defined by the clock signal in electrical circuit devices. As a result, an electrical circuit using the distorted clock signal can have smaller timing windows in which to transfer and/or process data, which could lead to reduced pulse widths, data errors, and unreliable circuit performance. As input/output speeds increase (e.g., as the cycles of a clock signal are reduced), it also becomes increasingly more challenging to reduce duty cycle distortion, meaning that the consequences of duty cycle distortion at high input/output speeds are even more apparent. In addition, electrical circuits at different locations (e.g., on different electrical circuit dies) can experience varying degrees of duty cycle distortion of a clock signal due to differing sources of distortion located along the corresponding clock branches of a clock tree that define the clock signal pathways. Thus, it is desirable to mitigate duty cycle distortion of a clock signal at points along the clock signal pathways closest to electrical circuits, especially as input/output speeds increase.